b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
68 lines
1.4 KiB
Python
68 lines
1.4 KiB
Python
__all__ = ["BaseProcess", "BaseSignalState", "BaseSimulation", "BaseEngine"]
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class BaseProcess:
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__slots__ = ()
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def __init__(self):
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self.reset()
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def reset(self):
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self.runnable = False
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self.passive = True
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def run(self):
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raise NotImplementedError
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class BaseSignalState:
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__slots__ = ()
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signal = NotImplemented
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curr = NotImplemented
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next = NotImplemented
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def set(self, value):
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raise NotImplementedError
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class BaseSimulation:
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def reset(self):
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raise NotImplementedError
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def get_signal(self, signal):
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raise NotImplementedError
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slots = NotImplemented
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def add_trigger(self, process, signal, *, trigger=None):
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raise NotImplementedError
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def remove_trigger(self, process, signal):
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raise NotImplementedError
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def wait_interval(self, process, interval):
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raise NotImplementedError
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class BaseEngine:
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def add_coroutine_process(self, process, *, default_cmd):
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raise NotImplementedError
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def add_clock_process(self, clock, *, phase, period):
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raise NotImplementedError
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def reset(self):
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raise NotImplementedError
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@property
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def now(self):
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raise NotImplementedError
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def advance(self):
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raise NotImplementedError
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def write_vcd(self, *, vcd_file, gtkw_file, traces):
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raise NotImplementedError
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