7df70059d1
The redesign introduces no fundamental incompatibilities, but it does
involve minor breaking changes:
* The simulator commands were moved from hdl.ast to back.pysim
(instead of only being reexported from back.pysim).
* back.pysim.DeadlineError was removed.
Summary of changes:
* The new simulator compiles HDL to Python code and is >6x faster.
(The old one compiled HDL to lots of Python lambdas.)
* The new simulator is a straightforward, rigorous implementation
of the Synchronous Reactive Programming paradigm, instead of
a pile of ad-hoc code with no particular design driving it.
* The new simulator never raises DeadlineError, and there is no
limit on the amount of delta cycles.
* The new simulator robustly handles multiclock designs.
* The new simulator can be reset, such that the compiled design
can be reused, which can save significant runtime with large
designs.
* Generators can no longer be added as processes, since that would
break reset(); only generator functions may be. If necessary,
they may be added by wrapping them into a generator function;
a deprecated fallback does just that. This workaround will raise
an exception if the simulator is reset and restarted.
* The new simulator does not depend on Python extensions.
(The old one required bitarray, which did not provide wheels.)
Fixes #28.
Fixes #34.
Fixes #160.
Fixes #161.
Fixes #215.
Fixes #242.
Fixes #262.
51 lines
1.4 KiB
Python
51 lines
1.4 KiB
Python
import functools
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import inspect
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from collections.abc import Iterable
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from ...hdl.cd import ClockDomain
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from ...back.pysim import *
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__all__ = ["run_simulation", "passive"]
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def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name=None,
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special_overrides={}):
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assert not special_overrides
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if hasattr(fragment_or_module, "get_fragment"):
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fragment = fragment_or_module.get_fragment()
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else:
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fragment = fragment_or_module
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if not isinstance(generators, dict):
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generators = {"sync": generators}
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fragment.domains += ClockDomain("sync")
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sim = Simulator(fragment)
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for domain, period in clocks.items():
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sim.add_clock(period / 1e9, domain=domain)
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for domain, processes in generators.items():
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def wrap(process):
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def wrapper():
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yield from process
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return wrapper
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if isinstance(processes, Iterable) and not inspect.isgenerator(processes):
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for process in processes:
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sim.add_sync_process(wrap(process), domain=domain)
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else:
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sim.add_sync_process(wrap(processes), domain=domain)
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if vcd_name is not None:
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with sim.write_vcd(vcd_name):
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sim.run()
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else:
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sim.run()
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def passive(generator):
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@functools.wraps(generator)
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def wrapper(*args, **kwargs):
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yield Passive()
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yield from generator(*args, **kwargs)
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return wrapper
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