7df70059d1
The redesign introduces no fundamental incompatibilities, but it does
involve minor breaking changes:
* The simulator commands were moved from hdl.ast to back.pysim
(instead of only being reexported from back.pysim).
* back.pysim.DeadlineError was removed.
Summary of changes:
* The new simulator compiles HDL to Python code and is >6x faster.
(The old one compiled HDL to lots of Python lambdas.)
* The new simulator is a straightforward, rigorous implementation
of the Synchronous Reactive Programming paradigm, instead of
a pile of ad-hoc code with no particular design driving it.
* The new simulator never raises DeadlineError, and there is no
limit on the amount of delta cycles.
* The new simulator robustly handles multiclock designs.
* The new simulator can be reset, such that the compiled design
can be reused, which can save significant runtime with large
designs.
* Generators can no longer be added as processes, since that would
break reset(); only generator functions may be. If necessary,
they may be added by wrapping them into a generator function;
a deprecated fallback does just that. This workaround will raise
an exception if the simulator is reset and restarted.
* The new simulator does not depend on Python extensions.
(The old one required bitarray, which did not provide wheels.)
Fixes #28.
Fixes #34.
Fixes #160.
Fixes #161.
Fixes #215.
Fixes #242.
Fixes #262.
103 lines
3.3 KiB
Python
103 lines
3.3 KiB
Python
# nmigen: UnusedElaboratable=no
|
|
|
|
from .utils import *
|
|
from ..hdl import *
|
|
from ..back.pysim import *
|
|
from ..lib.cdc import *
|
|
|
|
|
|
class FFSynchronizerTestCase(FHDLTestCase):
|
|
def test_stages_wrong(self):
|
|
with self.assertRaises(TypeError,
|
|
msg="Synchronization stage count must be a positive integer, not 0"):
|
|
FFSynchronizer(Signal(), Signal(), stages=0)
|
|
with self.assertRaises(ValueError,
|
|
msg="Synchronization stage count may not safely be less than 2"):
|
|
FFSynchronizer(Signal(), Signal(), stages=1)
|
|
|
|
def test_basic(self):
|
|
i = Signal()
|
|
o = Signal()
|
|
frag = FFSynchronizer(i, o)
|
|
|
|
sim = Simulator(frag)
|
|
sim.add_clock(1e-6)
|
|
def process():
|
|
self.assertEqual((yield o), 0)
|
|
yield i.eq(1)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 0)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 0)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 1)
|
|
sim.add_process(process)
|
|
sim.run()
|
|
|
|
def test_reset_value(self):
|
|
i = Signal(reset=1)
|
|
o = Signal()
|
|
frag = FFSynchronizer(i, o, reset=1)
|
|
|
|
sim = Simulator(frag)
|
|
sim.add_clock(1e-6)
|
|
def process():
|
|
self.assertEqual((yield o), 1)
|
|
yield i.eq(0)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 1)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 1)
|
|
yield Tick()
|
|
self.assertEqual((yield o), 0)
|
|
sim.add_process(process)
|
|
sim.run()
|
|
|
|
|
|
class ResetSynchronizerTestCase(FHDLTestCase):
|
|
def test_stages_wrong(self):
|
|
with self.assertRaises(TypeError,
|
|
msg="Synchronization stage count must be a positive integer, not 0"):
|
|
ResetSynchronizer(Signal(), stages=0)
|
|
with self.assertRaises(ValueError,
|
|
msg="Synchronization stage count may not safely be less than 2"):
|
|
ResetSynchronizer(Signal(), stages=1)
|
|
|
|
def test_basic(self):
|
|
arst = Signal()
|
|
m = Module()
|
|
m.domains += ClockDomain("sync")
|
|
m.submodules += ResetSynchronizer(arst)
|
|
s = Signal(reset=1)
|
|
m.d.sync += s.eq(0)
|
|
|
|
sim = Simulator(m)
|
|
sim.add_clock(1e-6)
|
|
def process():
|
|
# initial reset
|
|
self.assertEqual((yield s), 1)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 1)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 1)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 0)
|
|
yield Tick(); yield Delay(1e-8)
|
|
|
|
yield arst.eq(1)
|
|
yield Delay(1e-8)
|
|
self.assertEqual((yield s), 0)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 1)
|
|
yield arst.eq(0)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 1)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 1)
|
|
yield Tick(); yield Delay(1e-8)
|
|
self.assertEqual((yield s), 0)
|
|
yield Tick(); yield Delay(1e-8)
|
|
sim.add_process(process)
|
|
with sim.write_vcd("test.vcd"):
|
|
sim.run()
|