14 commits

Author	SHA1	Message	Date
whitequark	dbbcc49a71	hdl.ast: Cat.{operands→parts}	2018-12-18 19:15:50 +00:00
whitequark	7341d0d7ef	hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.	2018-12-18 16:13:29 +00:00
whitequark	c7f9386eab	fhdl.ir: add black-box fragments, fragment parameters, and Instance.	2018-12-17 22:55:39 +00:00
whitequark	8d1639a5a8	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
whitequark	8c4de99c0d	hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.	2018-12-17 17:21:29 +00:00
whitequark	850674637a	back.rtlil: implement Array.	2018-12-17 01:15:23 +00:00
whitequark	87cd045ac3	back.rtlil: implement Part.	2018-12-17 01:05:08 +00:00
whitequark	286a8009c8	compat.fhdl: reexport Array.	2018-12-16 10:39:54 +00:00
whitequark	d4e8d3e95a	back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.	2018-12-16 10:31:42 +00:00
whitequark	20a04bca88	back.pysim: implement Part.	2018-12-15 20:58:06 +00:00
whitequark	54fb999c99	back.pysim: implement ArrayProxy.	2018-12-15 19:37:36 +00:00
whitequark	80c5343600	hdl.ast: implement Array and ArrayProxy.	2018-12-15 17:16:31 +00:00
whitequark	f603b735e8	hdl.ast: improve ClockSignal, ResetSignal documentation.	2018-12-15 14:58:31 +00:00
whitequark	790eb05a92	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00

Renamed from nmigen/fhdl/ast.py (Browse further)