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Author SHA1 Message Date
whitequark d964ba9cc4 build,vendor: never carry around parts of differential signals. 
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
 2020-07-31 18:41:59 +00:00
whitequark 6bfff25e76 vendor: yosys is not a required tool for proprietary toolchains. 
Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.

Fixes #419.
 2020-07-02 18:13:54 +00:00
whitequark 706eb03e6b vendor.lattice_machxo2: add back as a compatibility shim. 2020-06-21 17:28:01 +00:00
Gwenhael Goavec-Merou 0aef5f4d48
vendor.lattice_machxo*: add MachXO3L support. 2020-06-21 17:24:47 +00:00
Renamed from nmigen/vendor/lattice_machxo2.py (Browse further)