56 commits

Author	SHA1	Message	Date
whitequark	d4e8d3e95a	back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.	2018-12-16 10:31:42 +00:00
whitequark	20a04bca88	back.pysim: implement Part.	2018-12-15 20:58:06 +00:00
whitequark	54fb999c99	back.pysim: implement ArrayProxy.	2018-12-15 19:37:36 +00:00
whitequark	80c5343600	hdl.ast: implement Array and ArrayProxy.	2018-12-15 17:16:31 +00:00
whitequark	f603b735e8	hdl.ast: improve ClockSignal, ResetSignal documentation.	2018-12-15 14:58:31 +00:00
whitequark	790eb05a92	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00

Renamed from nmigen/fhdl/ast.py (Browse further)