From c83b51db6daf3b73fb2406fdeecf6ef7486bb0be Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 26 Jan 2022 21:56:00 -0500 Subject: [PATCH] back.verilog: Fix strip_internal_attrs Fix the strip_internal_attrs parameter to verilog.convert by passing it down the call stack as intended. Signed-off-by: Alyssa Rosenzweig --- amaranth/back/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amaranth/back/verilog.py b/amaranth/back/verilog.py index 62c7192..7a0a8e5 100644 --- a/amaranth/back/verilog.py +++ b/amaranth/back/verilog.py @@ -48,5 +48,5 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru warnings.warn("Implicit port determination is deprecated, specify ports explictly", DeprecationWarning, stacklevel=2) fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs) - verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src) + verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs) return verilog_text